
module FeedbackMemory(
  input  wire        clk,
  input  wire        rst_n,
  input  wire        wr,
  input  wire [ 3:0] waddr,
  input  wire [ 9:0] wdata,
  input  wire [ 3:0] raddr,
  output reg  [ 9:0] rdata
);


reg[9:0] data_array_0;
reg[9:0] data_array_1;
reg[9:0] data_array_2;
reg[9:0] data_array_3;
reg[9:0] data_array_4;
reg[9:0] data_array_5;
reg[9:0] data_array_6;
reg[9:0] data_array_7;
reg[9:0] data_array_8;

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_0 <= #1 10'b0;
    else if(wr && (waddr==4'd0))
	data_array_0 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_1 <= #1 10'b0;
    else if(wr && (waddr==4'd1))
	data_array_1 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_2 <= #1 10'b0;
    else if(wr && (waddr==4'd2))
	data_array_2 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_3 <= #1 10'b0;
    else if(wr && (waddr==4'd3))
	data_array_3 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_4 <= #1 10'b0;
    else if(wr && (waddr==4'd4))
	data_array_4 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_5 <= #1 10'b0;
    else if(wr && (waddr==4'd5))
	data_array_5 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_6 <= #1 10'b0;
    else if(wr && (waddr==4'd6))
	data_array_6 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_7 <= #1 10'b0;
    else if(wr && (waddr==4'd7))
	data_array_7 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data_array_8 <= #1 10'b0;
    else if(wr && (waddr==4'd8))
	data_array_8 <= #1 wdata;
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	rdata <= #1 10'b0;
    else
	case(raddr)
        4'd0   : rdata <= #1 data_array_0;
        4'd1   : rdata <= #1 data_array_1;
        4'd2   : rdata <= #1 data_array_2;
        4'd3   : rdata <= #1 data_array_3;
        4'd4   : rdata <= #1 data_array_4;
        4'd5   : rdata <= #1 data_array_5;
        4'd6   : rdata <= #1 data_array_6;
        4'd7   : rdata <= #1 data_array_7;
        4'd8   : rdata <= #1 data_array_8;
	default: rdata <= #1 10'b0;
        endcase		
end

endmodule
